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Features
* JEDEC Standard VDD/VDDQ=1.8V 0.1V. * All inputs and outputs are compatible with SSTL_18 interface. * Fully differential clock inputs (CK,/CK) operation. * 8 Banks * Posted CAS * Burst Length: 4 and 8. * Programmable CAS Latency (CL): 3, 4 and 5. * Programmable Additive Latency (AL): 0, 1, 2, 3 and 4. * Write Latency (WL) =Read Latency (RL) -1. * Read Latency (RL) = Programmable Additive Latency (AL) + CAS Latency (CL) * Bi-directional Differential Data Strobe (DQS). * Data inputs on DQS centers when write. * Data outputs on DQS, /DQS edges when read. * On chip DLL align DQ, DQS and /DQS transition with CK transition. * DM mask write data-in at the both rising and falling edges of the data strobe. * Sequential & Interleaved Burst type available. * Off-Chip Driver (OCD) Impedance Adjustment * On Die Termination (ODT) * Auto Refresh and Self Refresh * 8,192 Refresh Cycles / 64ms * Average Refresh Period 7.8us at lower than Tcase 85C, 3.9us at 85C < Tcase 95C * RoHS Compliance * Partial Array Self-Refresh (PASR) * High Temperature Self-Refresh rate enable
EM44CM1688LBA
1Gb (8Mx8Bankx16) Double DATA RATE 2 SDRAM
Description
The EM44CM1688LBA is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 1,073,741,824 bits which organized as 8Mbits x 8 banks by 16 bits. This synchronous device achieves high speed double-data-rate transfer rates of up to 667 Mb/sec/pin (DDR2-667) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) Off-Chip Driver (OCD) impedance adjustment and On Die Termination (4) normal and weak strength data output driver. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 1Gb DDR2 device operates with a single power supply: 1.8V 0.1V VDD and VDDQ. Available package: TFBGA-84Ball (13mmx9mm, 0.8mm x 0.8mm ball pitch).
Ordering Information
Part No
EM44CM1688LBA-25F
Organization
64M X 16
Max. Freq
tCK 5: DDR2-800Mhz 5-5-5 ( Note )
Package
TFBGA-84 Ball
Grade
Commercial
Pb
Free
Note : Speed ( tCK *) is in order of CL-tRCD-tRP
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EM44CM1688LBA
* EOREX reserves the right to change products or specification without notice.
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Pin Assignment: Top View
1 VDD DQ14(UDQ6) VDDQ DQ12(UDQ4) VDD DQ6(LDQ6) VDDQ DQ4(LDQ4) VDDL NC VSSQ DQ9(UDQ1) VSSQ NC VSSQ DQ1(LDQ1) VSSQ VREF CKE BA2 BA0 A10/AP VSS A3 A7 VDD A12 2 VSS UDM VDDQ DQ11(UDQ3) VSS LDM VDDQ DQ3(LDQ3) VSS /WE BA1 A1 A5 A9 NC 3 A B C D E F G H J K L M N P R VSSQ UDQS VDDQ
EM44CM1688LBA
7
8 /UDQS VSSQ DQ8(UDQ0) VSSQ /LDQS VSSQ DQ0(LDQ0) VSSQ CK /CK /CS A0 A4 A8 NC VSS VDD
9 VDDQ DQ15(UDQ7) VDDQ DQ13(UDQ5) VDDQ DQ7(LDQ7) VDDQ DQ5(LDQ5) VDD ODT
DQ10(UDQ2) VSSQ LDQS VDDQ DQ2(LDQ2) VSSDL /RAS /CAS A2 A6 A11 NC
84ball TFBGA / (13.0mm x 9mm x 1.2mm) Note: 1. VDDL and VSSDL are power and ground for the DLL. 2. In case of only 8 DQs out of 16 DQs are used, LDQS, LDQSB and DQ0~7 must be used.
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Pin Description (Simplified)
Pin Name J8,K8 CK,/CK
EM44CM1688LBA
Function (System Clock) CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). (Chip Select) All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. (Clock Enable) CKE high activates and CKE low deactivates internal clock signals and device input buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self- Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for Self-Refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during Power Down. Input buffers, excluding CKE are disabled during Self-Refresh. (Address) Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged. A0~A12:Row address ; A0~9 :Column address. The address inputs also provide the op-code during Mode Register Set commands. (Bank Address) BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied (For 256Mb and 512Mb, BA2 is not applied). Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. (On Die Termination) ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal. The ODT pin will be ignored if the Extended Mode Register (EMRS(1)) is programmed to disable ODT. (Command Inputs) /RAS, /CAS and /WE (along with /CS) define the command being entered. (Data Strobe) Output with read data, input with write data. Edge-aligned with read data, centered in write data. LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. The data strobes LDQS and UDQS may be used in single ended mode or paired with optional complementary signals /LDQS and /UDQS
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L8
/CS
K2
CKE
M8,M3,M7,N2,N8, N3,N7,P2,P8,P3, M2,P7,R2
A0~12
L2,L3,L1
BA0, BA1,BA2
K9
ODT
K7, L7, K3
/RAS, /CAS, /WE
B7,A8,F7,E8
UDQS,/UDQS, LDQS,/LDQS
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EM44CM1688LBA
to provide differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or disables all complementary data strobe signals. In this data sheet, "differential DQS signals" refers to A10 = 0 of EMRS(1) using LDQS/LDQS and UDQS/UDQS. "single-ended DQS signals" refers to A10 = 1 of EMRS(1) using LDQS and UDQS. (Input Data Mask) DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. (Data Input/Output) Data inputs and outputs are on the same pin. (Power Supply/Ground) VDD and VSS are power supply for internal circuits. (DQ Power Supply/DQ Ground) VDDQ and VSSQ are power supply for the output buffers. (DLL Power Supply/DLL Ground) VDDL and VSSDL are power supply for DLL circuits (Reference Voltage) SSTL_1.8 reference voltage (No Connection) No internal electrical connection is present.
B3,F3
UDM,LDM
G8,G2,H7,H3,H1, H9,F1,F9,C8, C2,D7,D3,D1, D9,B1,B9 A1,E1,J9,M9,R1/ A3,E3,J3,N1,P9 A9,C1,C3,C7,C9,E 9,G1,G3,G7,G9/ A7,B2,B8,D2,D8,E 7,F2,F8,H2,H8 J1/J7 J2 A2,E2,L1,R3,R7, R8
DQ0~15
VDD/VSS
VDDQ/VSSQ
VDDL/VSSDL VREF NC
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Absolute Maximum Rating
Symbol VIN, VOUT VDD, VDDQ, VDDL, TOP TSTG PD Item Input, Output Voltage Power Supply Voltage DLL Power Supply Voltage Operating Temperature Range Storage Temperature Range Power Dissipation
EM44CM1688LBA
Rating -0.5 ~ +2.3 -0.5 ~ +2.3 -0.5 ~ +2.3 0 ~ +85 -55 ~ +100 1
Units V V V C C W
IOS Short Circuit Current 50 mA Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Capacitance (VCC=1.8V 0.1V, f=1MHz, TA=25C)
Symbol CCK CDCK CI CDI CIO CDIO Parameter Input Capacitance of CK, /CK Input Capacitance delta of CK, /CK Input Capacitance for others: CKE, Address, /CS, /RAS, /CAS, /WE Input Capacitance delta for others Input/Output Capacitance DQ, DM, DQS, DQS, RDQS, RDQS Input/Output Capacitance delta DDR2-667/533 Min. 1.0 1.0 2.5 Max. 2.0 0.25 2.0 0.25 4 0.5 DDR2-800 Min. 1.0 1.0 2.5 Max. 2.0 0.25 1.75 0.25 3.5 0.5 pF pF pF pF pF pF Units
Recommended DC Operating Conditions (TA=0C ~85C)
Symbol VDD VDDDL VDDQ VREF VTT VID VIH Parameter Power Supply Voltage Power Supply for DLL Voltage Power Supply for Output Voltage Input Reference Voltage Termination Voltage DC differential Input Voltage Input Logic High Voltage Min. 1.7 1.7 1.7 0.49* VDDQ VREF - 0.04 0.25 VREF +0.125 -0.3 Typ. 1.8 1.8 1.8 0.5* VDDQ VREF Max. 1.9 1.9 1.9 0.51* VDDQ VREF +0.04 VDDQ+0.6 VDDQ+0.3 VREF - 0.125 Units V V V V V V V V
VIL Input Logic Low Voltage Note: * All voltages referred to VSS.
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Recommended DC Operating Conditions
(VDD=1.8V0.1V, TA=0C ~ 85C) Symbol Parameter Operating Current
(Note 1)
EM44CM1688LBA
Test Conditions Burst length=2, tRCtRC(min.), IOL=0mA, One bank active CKEVIL(max.), tCK=min CKEVIH(min.), tCK=min, /CSVIH(min.) Input signals SWITCHING CKEVIL(max.), tCK=min CKEVIL(max.), tCK=min CKEVIH(min.), tCK=min, /CSVIH(min.) Input signals SWITCHING tCK tCK(min.), IOL=0mA, All banks active tRC tRFC (min.), All banks active CKE0.2V All bank Interleave read
-5 3-3-3 Max. 100 10
-37 4-4-4 Max. 115 10
-3 5-5-5 Max. 115 10
Units
IDD1 IDD2P
mA mA
Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-power Down Mode Active Standby Current in Power Down Mode (A12=0) Active Standby Current in Power Down Mode (A12=1) Active Standby Current in Non-power Down Mode Operating Current (Note 2) (Burst Mode) Refresh Current (Note 3) (Burst Mode) Self Refresh Current Operating Current
IDD2N
65
70
80
mA
IDD3P IDD3P
26 13
30 13
30 13
mA mA
IDD3N
60
67
70
mA
IDD4 IDD5 IDD6 IDD7
135 165 11 230
155 175 11 245
170 175 11 250
mA mA mA mA
*All voltages referenced to VSS. Note 1: IDD1 depends on output loading and cycle rates. (CL=CL min. AL=0) Note 2: IDD4 depends on output loading and cycle rates. Input signals SWITCHING. Note 3: Min. of tRFC (Auto refresh Row Cycle Times) is shown at AC Characteristics.
Recommended DC Operating Conditions (Continued)
Symbol IIL IOL VOH VOL Parameter Input Leakage Current Output Leakage Current High Level Output Voltage Low Level Output Voltage Test Conditions 0VIVDDQ, VDDQ=VDD All other pins not under test=0V 0VOVDDQ, DOUT is disabled IO=-13.4mA IO=+13.4mA Min. -2 -5 VTT+0.603 VTT-0.603 Max. +2 +5 Units uA uA V V
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Block Diagram
EM44CM1688LBA
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OCD Default Setting Table
Symbol Parameter Output Impedance Pull-up / Pull down mismatch Output Impedance step size for OCD calibration Output Slew Rate Min. 0 0 +1.5
EM44CM1688LBA
Typ. -
Max. 23.4 4 1.5 5.0
Units V/ns
AC Operating Test Conditions
(VDD=1.8V 0.1V, TA=0C ~85C) Symbol VSWING(max) SLEW VREF Item Input Signal maximum peak to peak swing Input Signals minimum slew rate Input Reference Level Conditions 1.0 V 1.0 V/ns 0.5*VDDQ
AC Operating Test Conditions(Continued)
Symbol VID VIX VOX VOH VOL Parameter AC differential Input Voltage AC differential corss point Input Voltage AC differential corss point Output Voltage High Level Output Voltage Low Level Output Voltage Min. 0.5 0.5*VDDQ - 0.175 0.5*VDDQ - 0.125 VTT+0.603 Max. VDDQ+0.6 0.5*VDDQ + 0.175 0.5*VDDQ + 0.125 VTT-0.603 Units V V V V V
Symbol VIH VIL
Parameter Input Logic High Voltage Input Logic Low Voltage
DDR2-667/533 Min. VREF + 0.25 Max. VREF - 0.25
DDR2-800 Min. VREF + 0.2 Max. VREF - 0.2
Units V V
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AC Operating Test Characteristics
(VDD=1.8V0.1V, TA=0C ~85C) Symbol tDQCK tDQSCK tCL,tCH Parameter DQ output access from CLK,/CLK DQS output access time from CLK,/CLK CL low/high level width CAS Latency =5 Clock Cycle CAS Latency Time =4 CAS Latency =3 DQ and DM setup time DQ and DM hold time DQ and DM input pulse width for each input Data out high impedance time from CLK,/CLK Data out low impedance time from CLK,/CLK DQS-DQ skew for associated DQ signal Data hold skew factor Write command to first latching DQS transition DQS Low/High input pulse width DQS input valid window Mode Register Set command cycle time Write Preamble setup time Write Preamble Write Postamble Address/control input setup time Address/control input hold time Read Preamble Min. -0.4 -0.35 0.48 2.5 3.75 5 50 125 0.35
-0.4 -0.4
EM44CM1688LBA
-25 Max. +0.4 +0.35 0.52 8 8 8 +0.4 +0.4
Units ns ns tCK ns ns ns ps ps tCK ns ns ns ns tCK tCK tCK tCK ns tCK tCK ns ns tCK
tCK
tDS tDH tDIPW tHZ tLZ tDQSQ tQSH tDQSS tDQSL,tDQSH tDSL,tDSH tMRD tWPRES tWPRE tWPST tIS tIH tRPRE
WL -0.25
0.2 0.34
WL +0.25
0.35 0.2 2 0 0.35 0.4 0.175 0.25 0.9
0.6 1.1
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(VDD=1.8V0.1V, TA=0C ~85C) Symbol tRPST tRAS tRC tRFC tRCD tRP tRRD tCCD tWR tDAL tXSRD tXSNR tXARD tXARDS tXP tWTR tRTP tCKE tWPD tRPD tOIT tREFI Parameter Read Postamble Active to Precharge command period Active to Active command period Auto Refresh Row Cycle Time Active to Read or Write delay Precharge command period Active bank A to B command period Column address to column address delay Write recovery time Auto Pre-charge write recovery + pre-charge time Exit self refresh to Read command Exit self refresh to non-read command Exit active power-down mode to Read command (Fast exit) Exit active power-down mode to Read command (Slow exit) Exit pre-charge power-down to any non-read command Internal Write to Read command delay Internal Read to pre-charge delay CKE minimum pulse width Write to pre-charge delay(same bank) Read to pre-charge delay(same bank) OCD drive mode output delay Average periodic refresh interval -3 Min. 0.4 45 57.5 127.5 12.5 12.5 10 2 15 tRP+ tWR 200 137.5 2 8-AL 2 7.5 7.5 3
WL+ BL/2 +
EM44CM1688LBA
AC Operating Test Characteristics (Continued)
Unit Max. 0.6 70K 12 7.8 tCK ns ns ns ns ns ns tCK ns tCK tCK ns tCK tCK tCK ns ns tCK tCK tCK ns us
tWR
AL+ BL/2+1
0 -
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(VDD=1.8V0.1V, TA=0C ~85C) Symbol tAOND tAOFD tAON tAOF tAONPD Parameter ODT turn-on delay ODT turn-off delay ODT turn-on ODT turn-off
(Note 1)
EM44CM1688LBA
AC Operating Test Characteristics (Continued)
-3 Min. 2 2.5
tAC (MIN) tAC (MIN) tAC (MIN) + 2ns tAC (MIN) + 2ns tAC (MAX) + 0.7 tAC (MAX) + 0.6 2Tck+ tAC (MAX) + 1ns
2.5Tck
Unit Max. tCK tCK ns ns
(Note 2)
ODT turn-on (Power-Down Modes)
ns
tAOFPD
ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
+ tAC (MAX) + 1ns
ns
tANPD tAXPD
3 8
-
tCK tCK
Note 1: ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND.
Note 2: ODT turn off time min is when the device starts to turn off ODT resistance
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
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Simplified State Diagram
EM44CM1688LBA
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1. Command Truth Table
Command Ignore Command No Operation Read Read with Auto Pre-charge Write Write with Auto Pre-charge Bank Activate Pre-charge Select Bank Pre-charge All Banks (Ext.) Mode Register Set Symbol CKE n-1 n /CS /RAS
EM44CM1688LBA
BA0, BA1
/CAS
/WE
A10
A12~A0
DESL NOP READ READA WRIT WRITA ACT PRE PALL
H H H H H H H H H
X X H H H H H H H
H L L L L L L L L
X H H H H H L L L
X H L L L L H H H
X H H H L L H L L
X X V V V V V V X
X X L H L H V L H
X X V V V V V X X V
(E)MRS H H L L L L V V H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
2. CKE Truth Table
Item Idle Idle Self Refresh Idle Power Down Command CBR Refresh Command Self Refresh Entry Self Refresh Exit Power Down Entry Power Down Exit Symbol REF SELF CKE n-1 n HH H L L H H L L H H L L H /CS L L L H H L H /RAS L L H X X H X H /CAS L L H X X H X H /WE H H H X X H X H Addr. X X X X X X X X
L H L Remark H = High level, L = Low level, X = High or Low level (Don't care)
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3. Operative Command Table
Current State /CS
H L L Idle L L L L L H L L Row Active L L L L L H L L L Read L L L L H L L L L L L L X H H H H H L L X H H L H L H L X H L H BA/RA BA, A10 X Op-Code, Mode-Add X X X BA/CA/A10 ACT PRE/PREA REFA MRS DESL NOP TERM READ/READA
EM44CM1688LBA
/R
X H H H L L L L X H H H L L L L X H H H
/C
X H H L H H L L X H H L H H L L X H H L
/W
X H L X H L H L X H L L H L H L X H L H
Addr.
X X X BA/CA/A10 BA/RA BA, A10 X Op-Code, Mode-Add X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10
Command
DESL NOP TERM READ/WRIT/BW ACT PRE/PREA REFA MRS DESL NOP READ/READA WRIT/WRITA ACT PRE/PREA REFA MRS DESL NOP TERM READ/READA
Action NOP NOP NOP ILLEGAL
(Note 1)
Bank active,Latch RA NOP (Note 4) Auto refresh Mode register NOP NOP Begin read,Latch CA, Determine auto-precharge Begin write,Latch CA, Determine auto-precharge ILLEGAL Precharge/Precharge all ILLEGAL ILLEGAL NOP(Continue burst to end) NOP(Continue burst to end) Terminal burst Terminate burst,Latch CA, Begin new read, Determine Auto-precharge ILLEGAL
(Note 1) (Note 1) (Note 3)
Terminate burst, PrecharE ILLEGAL ILLEGAL NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL Terminate burst with DM="H",Latch CA,Begin read,Determine (Note 2) auto-precharge Terminate burst,Latch CA,Begin new write, Determine (Note 2) auto-precharge ILLEGAL
(Note 1)
Write
L L L L L
H L L L L
L H H L L
L H L H L
BA/CA/A10 BA/RA BA, A10 X Op-Code,
WRIT/WRITA ACT PRE/PREA REFA MRS
Terminate burst with DM="H", Precharge ILLEGAL ILLEGAL
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Current State /CS
H L L L L L L L H L L L Write with AP L L L L H L L L Pre-charging L L L L H L L L L L L L
EM44CM1688LBA
3. Operative Command Table (Continued)
/R
X H H H L L L L X H H H L L L L X H H H L L L L X H H H L L L L
/C
X H H L H H L L X H H L H H L L X H H L H H L L X H H L H H L L
/W
X H L X H L H L X H L X H L H L X H L X H L H L X H L X H L H L
Addr.
X X BA/CA/A10 BA/RA BA/A10 X X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add
Command
DESL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS DESL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS DESL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS DESL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS
Action NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL (Note 1) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL (Note 1) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(idle after tRP) NOP(idle after tRP) NOP (Note 1) ILLEGAL ILLEGAL (Note 3) NOP(idle after tRP) ILLEGAL ILLEGAL NOP(Row active after tRCD) NOP(Row active after tRCD) NOP (Note 1) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
(Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
Read with AP
Row Activating
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge
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Current State /CS
H L L L Write Recovering L L L L L H L L L L L L L
EM44CM1688LBA
3. Operative Command Table (Continued)
/R
X H H H H L L L L X H H H L L L L
/C
X H H L L H H L L X H H L H H L L
/W
X H L H L H L H L X H L X H L H L
Addr.
X X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add
Command
DESL NOP TERM READ WRIT/WRITA ACT PRE/PREA REFA MRS DESL NOP TERM READ/WRIT ACT PRE/PREA REFA MRS
Action NOP NOP NOP (Note 1) ILLEGAL New write, Determine AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(idle after tRP) NOP(idle after tRP) NOP ILLEGAL ILLEGAL NOP(idle after tRP) ILLEGAL ILLEGAL
(Note 1) (Note 1)
Refreshing
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Note 1: ILLEGAL to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. Note 2: Must satisfy bus contention, bus turn around, and/or write recovery requirements. Note 3: NOP to bank precharging or in idle state.May precharge bank indicated by BA. Note 4: ILLEGAL of any bank is not idle.
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4. Command Truth Table for CKE
Current State CKE n-1 n
H L L L L L L H L L L L L L H H H H H H H H H L Any State Other than Listed above H X H H H H H L X H H H H H L H L L L L L L L L X H
EM44CM1688LBA
/CS
X H L L L L X X H L L L L X X H L L L L L L L X X
/R
X X H H H L X X X H H H L X X X H H H L L L L X X
/C
X X H H L X X X X H H L X X X X H H L H L L L X X
/W
X X H L X X X X X H L X X X X X H L X H H L L X X
Addr.
X X X X X X X X X X X X X X X X X X X RA X Op-Code Op-Code X X
Action INVALID Exist Self-Refresh Exist Self-Refresh ILLEGAL ILLEGAL ILLEGAL NOP(Maintain self refresh) INVALID Exist Power down Exist Power down ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Power down) Refer to function true table (Note 3) Enter power down mode (Note 3) Enter power down mode ILLEGAL ILLEGAL Row active/Bank active (Note 3) Enter self-refresh Mode register access Special mode register access Refer to current state Refer to command truth table
Self Refresh
Both bank precharge power down
All Banks Idle
Remark: H = High level, L = Low level, X = High or Low level (Don't care) Notes 1: After CKE's low to high transition to exist self refresh mode.And a time of tRC(min) has to be Elapse after CKE's low to high transition to issue a new command. Notes 2:CKE low to high transition is asynchronous as if restarts internal clock. Notes 3:Power down and self refresh can be entered only from the idle state of all banks.
Feb. 2009 18/29
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Initialization
EM44CM1688LBA
The following sequence is required for power-up and initialization and is shown in below Figure: 1. Apply power and attempt to maintain CKE below 0.2 * VDDQ and ODT at a low state (all other inputs may be undefined). To guarantee ODT off, VREF must be valid and a low level must be applied to the ODTpin. - VDD,VDDL and VDDQ are driven from a single power converter output, AND VTT is limited to 0.95 V max, AND VREF tracks VDDQ/2 or - Apply VDD before or at the same time as VDDL; Apply VDDL before or at the same time as VDDQ; Apply VDDQ before or at the same time as VTT & VREF. at least one of these two sets of conditions must be met. 2. Start clock (CK, /CK) and maintain stable power and clock condition for a minimum of 200 s. 3. Apply NOP or Deselect commands & take CKE high. 4. Wait minimum of 400ns, then issue a Precharge-all command. 5. Issue Reserved command EMRS(2) or EMRS(3). 6. Issue EMRS(1) command to enable DLL. (A0=0 and BA0=1 and BA1=0) 7. Issue MRS command (Mode Register Set) for "DLL reset". (A8=1 and BA0=BA1=0) 8. Issue Precharge-All command. 9. Issue 2 or more Auto-Refresh commands. 10. Issue a MRS command with low on A8 to initialize device operation. (without resetting the DLL) 11. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD calibration is not used, EMRS OCD Default command (A9=A8=A7=1) followed by EMRS(1) OCD Calibration Mode Exit command (A9=A8=A7=0) must be issued with other parameters of EMRS(1). 12. The DDR2 SDRAM is now initialized and ready for normal operation.
Feb. 2009 19/29
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Mode Register Definition Mode Register Set
EM44CM1688LBA
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM which contains addressing mode, burst length, /CAS latency, WR (write recovery), test mode, DLL reset and various vendor's specific opinions. The defaults values of the register is not defined, so the mode register must be written after power up for proper DDR2 SDRAM operation. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE and BA0/1. The state of the address pins A0-A12 in the same cycle as /CS, /RAS, /CAS, /WE and BA0,1 going low is written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operating as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0-A2, addressing mode uses A3, /CAS latency ( read latency from column address ) uses A4-A6. A7 is used for test mode. A8 is used for DDR reset. A9 ~ A11 are used for write recovery time (WR) ,A7 must be set to low for normal MRS operation. With address bit A12 two Power-Down modes can be selected, a "standard mode" and a "low-power" Power-Down mode.
Feb. 2009 20/29
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Address input for Mode Register Set ( MRS )
BA1 0 BA0 0 A12 PD A11 A10 WR A9 A8 DLL A7 TM A6
EM44CM1688LBA
A5
A4
A3 BT
A2
A1
A0
CAS Latency
Burst Length
DLL Rest A8 No Yes 0 1
Mode Normal Test
A7 0 1
Burst Length 4 8
A2 0 0
A1 1 1
A0 0 1
Active Power-Down Fast Exit ( Normal ) Slow Exit ( low power )
A12 0 1
Burst Type Sequential Interleave
A3 0 1
Write Recovery Reserved 2 3 4 5 6 Reserved Reserved
A11 0 0 0 0 1 1 1 1
A10 0 0 1 1 0 0 1 1
A9 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved Reserved 3 4 5 Reserved Reserved
A6 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
BA1 0 0 1 1
BA0 0 1 0 1
MRS Mode Mode Register (MRS) Extended Mode Register / EMRS(1) EMRS(2) * Reserved EMRS(3) * Reserved
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Burst Type (A3)
Burst Length A3 X 4 X X X X X X 8 X X X X A2 X X X X 0 0 0 0 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 A0 0 1 0 1 0 1 0 1 0 1 0 0123 1230 2301 3012 01234567 12345670 23456701 34567012 45670123 56701234 67012345
EM44CM1688LBA
Sequential Addressing
Interleave Addressing 0123 1032 2301 3210 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210
X 1 1 1 70123456 * Page length is a function of I/O organization and column addressing
Write Recovery
WR (Write Recovery) is for Writes with Auto-Precharge only and defines the time when the device starts pre-charge internally. WR must be programmed to match the minimum requirement for the analogue tWR timing.
Power-Down Mode
Active power-down (PD) mode is defined by bit A12. PD mode allows the user to determine the active power-down mode, which determines performance vs. power savings. PD mode bit A12 does not apply to precharge power-down mode. When bit A12 = 0, standard Active Power-down mode or `fast-exit' active power-down mode is enabled. The tXARD parameter is used for `fast-exit' active power-down exit timing. The DLL is expected to be enabled and running during this mode. When bit M12 = 1, a lower power active power-down mode or `slow-exit' active power-down mode is enabled. The tXARDS parameter is used for `slow-exit' active power-down exit timing. The DLL can be enabled, but `frozen' during active power-down mode since the exit-to-READ command timing is relaxed. The power difference expected between PD `normal' and PD `low-power' mode is defined in the IDD table.
Feb. 2009 22/29
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EM44CM1688LBA
Address input for Extended Mode Register Set ( EMRS(1) )
The EMRS (1) is written by asserting low on /CS, /RAS, /CAS, /WE,BA1 and high on BA0 ( The DDR2 should be in all bank pre-charge with CKE already prior to writing into the extended mode register. ) The extended mode register EMRS(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency,OCD program, ODT, DQS and output buffers disable, RQDS and RDQS enable. The default value of the extended mode register EMRS(1) is not defined, therefore the extended mode register must be written after power-up for proper operation.The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the EMRS(1). Mode register contents can be changed using the same command and clock cycle requirements during normal operation when all banks are in pre-charge state. BA1 0 BA0 1 A12
Q off
A11
A10
A9
A8
A7
A6 Rtt
A5
A4 AL
A3
A2 Rtt
A1
D.I.C
A0 DLL
RDQS /DQS
OCD Program
Q off
Disable Enable
A12
/ DQS
Enable Disable
A10
Rtt
Disable
A6 0 0 1 1
A2 0 1 0 1
DLL Rest
Enable Disable
A0 0 1
0 1
0 1
75 150 50
Output buffers
RDQS, /RQDS Disable Enable
A11 0 1
I/O
Output Driver Impedence Control
A1 0 1
Normal (100%)
onlyX8
Weak ( 60%)
OCD
Operation Drive (1) Drive (0)
A9 0 0 0 1 1
(Note 2)
A8 0 0 1 0 1
A7 0 1 0 0 1
Additive Latency 0 1 2 3 4 5 Reserved Reserved
A5 0 0 0 0 1 1 1 1
A4 0 0 1 1 0 0 1 1
A3 0 1 0 1 0 1 0 1
OCD calibration mode exit
Adjust mode
(Note 1)
OCD Calibration default
BA1 0 0 1 1
Feb. 2009
BA0 0 1 0 1
MRS Mode Mode Register (MRS) Extended Mode Register / EMRS(1) EMRS(2) * Reserved EMRS(3) * Reserved
23/29
Note 1: When adjust mode is issued, AL from previously set value must be applied. Note 2: After setting to default, OCD mode needs to be exited by setting A9 ~A7 to 000. Refer to the chapter Off-Chip Driver (OCD) Impedance Adjustment for detailed information.
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Output Drive Strength
EM44CM1688LBA
The output drive strength is defined by bit A1. Normal drive strength outputs are specified to be SSTL_18. Programming bit A1 = 0 selects normal (100 %) drive strength for all outputs. Programming bit A1 = 1 will reduce all outputs to approximately 60 % of the SSTL_18 drive strength. This option is intended for the support of the lighter load and/or point-to-point environments.
Single-ended and Differential Data Strobe Signals
EMRS A11
(RDQS Enable)
Stobe Function Matrix A10 RDQS DM DM DM RDQS RDQS /RDQS Hi -Z Hi -Z /RDQS Hi -Z DQS DQS DQS DQS DQS /DQS /DQS Hi -Z /DQS Hi -Z
signals
(/DQS Enable)
0 ( Disable) 0 ( Disable) 1 ( Enable)
only for X8
0 ( Enable) 1 ( Disable) 0 ( Enable) 1 ( Disable)
differential DQS signals single-ended DQS signals differential DQS signals (for X8) single-ended DQS signals (for X8)
1 ( Enable)
only for X8
Output Disable ( Qoff )
Under normal operation, the DRAM outputs are enabled during Read operation for driving data (Qoff bit in the EMRS(1) is set to (0). When the Qoff bit is set to 1, the DRAM outputs will be disabled. Disabling the DRAM outputs allows users to measure IDD currents during Read operations, without including the output buffer current.
Feb. 2009 24/29
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BA1 1 BA0 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 SRF A6 0 0
EM44CM1688LBA
Address input for Extended Mode Register Set ( EMRS(2) ) * Reserved
A5 A4 0 A3 0 A2 A1 PASR A0
High Temperature Self-Refresh Rate Enable Disable Enable** (85C Tcase 95C)
A7 0 1
Partial Array Self Refresh Full array Half Array (BA[1:0]=00&01) Quarter Array (BA[1:0]=00) Not defined 3/4 array(BA[1:0]=01,10,&11) Half array (BA[1:0]=10&11) Quarter array (BA[1:0]=11) Not defined
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
BA1 0 0 1 1
BA0 0 1 0 1
MRS Mode Mode Register (MRS) Extended Mode Register / EMRS(1) EMRS(2) * Reserved EMRS(3) * Reserved
Address input for Extended Mode Register Set ( EMRS(3) ) * Reserved
BA1 1 BA0 1 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 0 A0 0
Feb. 2009 25/29
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On-Die Termination (ODT)
EM44CM1688LBA
ODT (On-Die Termination) is a new feature on DDR2 components that allows a DRAM to turn on/off termination resistance for each UDQ, LDQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal via the ODT control pin for x16 configuration, where UDQS and LDQS are terminated only when enabled in the EMRS(1) by address bit A10 = 0. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function can be used for all active and standby modes. ODT is turned off and not supported in SelfRefresh mode.
ODT Function
Switch sw1 or sw2 is enabled by the ODT pin. Selection between sw1 or sw2 is determined by "Rtt (nominal)" in EMRS(1) address bits A6 & A2. Target Rtt = 0.5 * Rval1 or 0.5 * Rval2. The ODT pin will be ignored if the EMRS(1) is programmed to disable ODT.
Feb. 2009 26/29
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EM44CM1688LBA
Off-Chip Driver (OCD) Impedance Adjustment
DR2 SDRAM supports driver calibration feature and the flow chart below is an example of the sequence. Every calibration mode command should be followed by "OCD calibration mode exit" before any other command being issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be carefully controlled depending on system environment.
Feb. 2009 27/29
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OCD impedance adjust
EM44CM1688LBA
To adjust output driver impedance, controllers must issue the ADJUST EMRS(1) command along with a 4 bit burst code to DDR2 SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via MRS command before activating OCD and controllers must drive the burst code to all DQs at the same time. DT0 is the table means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment can be up to 16 and when the limit is reached, further increment or decrement code has no effect. The default setting may be any step within the maximum step count range. When Adjust mode command is issued, AL from previously set value must be applied.
Off-Chip-Driver Adjust Program
4 bit burst code inputs to all DQs DT0 0 0 0 0 1 0 0 1 1 DT1 0 0 0 1 0 1 1 0 0 DT2 0 0 1 0 0 0 1 0 1 DT3 0 1 0 0 0 1 0 1 0 Operation Pull-up driver strength NOP (no operation) Increase by 1 step Decrease by 1 step NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Decrease by 1 step Reserved Pull-down driver strength NOP (no operation) NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step Decrease by 1 step Reserved
Other Combinations
Feb. 2009 28/29
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Package Description
( BGA-84 balls Package)
EM44CM1688LBA
Feb. 2009 29/29
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